The aarch64 instruction set has a madd instruction that performs integer multiply-adds. Cortex A725 and older Arm cores had dedicated integer multi-cycle pipes that could handle madd along with other complex integer instructions. Cortex X925 instead breaks madd into two micro-ops, and handles it with any of its four multiply-capable integer pipes. Likely, Arm wanted to increase throughput for that instruction without the cost of implementing three register file read ports for each multiply-capable pipe. Curiously, Arm’s optimization guide refers to the fourth scheduler’s pipes as “single/multi-cycle” pipes. “Multi-cycle” is now a misnomer though, because the core’s “single-cycle” integer pipes can handle multiplies, which have two cycle latency. On Cortex X925, “multi-cycle” pipes distinguish themselves by handling special operations and being able to access FP/vector related registers.
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外观方面，新 i3 将明显脱离现款 G20 3 系的设计脉络，转向 Neue Klasse（新世代）概念车所确立的更为锐利、几何感更强的方向。结合预告图与伪装车信息来看，新 i3 保留了传统三厢轿车的基本比例，但车身表面处理更为极致简洁，线条更加平滑流畅。